In a high speed data transmission system, the integration level of circuit modules becomes increasingly higher, and the size becomes smaller and smaller. Therefore, when designing an IC module, the designer needs to comprehensively consider influences of different aspects of the IC such as operation speed, power consumption and noise. The CMOS circuit has an advantage of low power consumption. However, the operation speed of the CMOS circuit is relatively low, and a relatively high noise tends to be produced. In contrast, the CML circuit has a high operation speed which is ten times higher than that of the CMOS circuit, and a low noise, but the power consumption of the CML circuit is relatively high. In a current design of a high speed System on Chip (SOC), the CMOS circuit and CML circuit are used in combination to compensate the disadvantage of each other. Since the CMOS circuit is a single-port input-output circuit with a rail-to-rail amplitude level, whereas the CML circuit is a dual port input-output circuit with low voltage differential signal, a converter needs to be employed between the CMOS circuit and the CML circuit, so as to implement the transition between the CMOS circuit and the CML circuit.
A differential circuit is a converter that is often employed from CMOS to CML. The differential circuit includes differential pair transistors, a pair of loads, and a biased transistor. Each transistor of the differential pair transistors has three terminals, i.e., an input terminal, a connection terminal and an output terminal. As shown in FIG. 1, a CMOS to CML converter is illustrated as an example, where differential pair transistors include a pair of transistors, and each transistor is an NMOS transistor. The circuit includes a pair of differential NMOS transistors M1 and M2 and a pair of loads i.e. resistor R1 and resistor R2. Generally, the resistance value of resistor R1 is equal to that of resistor R2. The current sink of the circuit is NMOS transistor M3, whose gate is connected to an external bias voltage Vbias. An output signal V2 of CMOS and a signal V1 that is obtained when V2 passes through an inverter 1 constitute a pair of differential signals. The pair of differential signals is used as the input signals B and A for the differential pair transistors M2 and M1. Referring to FIG. 2, in the traditional converter as shown in FIG. 1, when the input signals of the differential pair transistors M1 and M2 are in the transition phase t, the differential pair transistors M1 and M2 tends to be turned off simultaneously, so that the current IM3 in the biased transistor M3 that acts as a constant current source may be changed abruptly, and a peak tail current may be caused. The existence of the peak tail current may further affect the stability of the common mode voltage signals that are output from the signal output terminals Vo1 and Vo2 of the whole converter, so that the jitter of the converter is high.
The U.S. Pat. No. 7,038,495 discloses a low jitter high speed CMOS to CML clock converter, whose circuit is as shown in FIG. 3. This converter is an improvement of the traditional converter. The differential pair transistors in the converter include two pairs of differential transistors: M1 and M2, M11 and M22. Taking it as an example that the differential transistors are all NMOS transistors, the differential transistors in the converter include four differential NMOS transistors: M1, M11, M2 and M22. These four differential transistors are divided into two groups, and each group includes two differential transistors: M1 and M11, M2 and M22. In each group of the differential transistors M1 and M11 or M2 and M22, the source terminal of M1/M2, which is used as the connection terminal of the differential transistor, is connected with the source terminal of M11/M22, which is used as the connection terminal of the differential transistor, and the drain terminal of M1/M2, which is used as the output terminal of the differential transistor, is connected with the drain terminal of M11/M22, which is used as the output terminal of the differential transistor. A voltage with a phase of 0 degree is input to M1, a voltage with a phase of 90 degree is input to M11, a voltage with a phase of 180 degree is input to M2, and a voltage with a phase of 270 degree is input to M22. The input signals of M1 and M2 are a pair of differential signals with respect to each other, and the input signals of M11 and M22 are a pair of differential signals with respect to each other. The input voltage signals are as shown in FIG. 4. Within a change period of the output signal Vo1/Vo2, M1, M11, M2 and M22 are turned on in sequence. There are a plurality of transitions, i.e. the transition between M1 and M11, between M11 and M2, between M2 and M22 as well as between M22 and M1. The existence of the transitions between a plurality of input signals causes the peak tail current in the current IM3 of the biased transistor M3 to appear even more frequently within a change period of the output signal. Meanwhile, the common mode voltage signal output from the output terminal Vo1/Vo2 of the converter is unstable, and thus a high jitter is caused.